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| SSRAM Austin Semiconductor, Inc. 512K x 36 SSRAM Flow-Through SRAM No Bus Latency AVAILABLE AS MILITARY SPECIFICATIONS *MIL-STD-883 AS5SS512K36 PIN ASSIGNMENT (Top View) 100-Pin TSOP (DQ) FEATURES * Pin compatible and functionally equivalent to ZBT devices. * Supports 133MHz bus operations with zero wait states -Data is transferred on every clock * Internally self-timed output buffer control to eliminate the need to use asynchronous OE\ * Registered inputs for Flow-Through operation * Byte Write capability * Common I/O architecture * Fast clock-to-output times -7.5ns (for 133 MHz device)* -8.5ns (for 117 MHz device) * Single 3.3V -5% and +1-% power supply VDD * Separate VDD for 3.3V or 2.5V I/O * Clock Enable (CEN\) pin to suspend operation * Synchronous self-timed writes * Available in 100-pin TSOP package.** * Burst Capability - linear or interleaved burst order OPTIONS * Timing 7.5ns access 8.5ns access * Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) * Package(s)** 100-pin TSOP NOTES: MARKING -7.5* -8.5 XT IT DQ * 7.5ns speed available with IT option only. **Contact factory for BGA package interests. GENERAL DESCRIPTION The AS5SS512K36 is 3.3V, 512K by 36 Synchronous-FlowThrough Burst SRAMs, designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The AS5SS512K36 is equipped with the advanced no bus latency logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Read/Write transitions. The AS5SS512K36 is pin compatible and functionally equivalent to ZBT devices. AS5SS512K36 Rev. 0.2 04/09 All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN\) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWS\a,b,c,d) and a Write Enable (WE\) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Synchronous Chip Enable (CE1\, CE2, CE3\) and an asynchronous Output Enable (OE\) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. For more products and information please visit our web site at www.austinsemiconductor.com Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SSRAM Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM AS5SS512K36 SELECTION GUIDE Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 7.5 190 70 117 MHz 8.5 175 70 UNITS ns mA mA AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SSRAM Austin Semiconductor, Inc. AS5SS512K36 PIN DEFINITIONS PIN AO A1 A BWSa\ BWSb\ BWSc\ BWSd\ WE\ I/O TYPE InputSynchronous DESCRIPTION Address inputs used to select one of the 532,288 address locations. Sampled at the rising edge of the CLK. Byte write select inputs, active LOW. Qualified with WE\ to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa\ controls DQa and DPa, BWSb\ controls DQb and DPb, BWSc\ controls DQc and DPc, BWSd\ controls DQd and DPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN\ is active LOW. This signal must be asserted LOW to initiate a write sequence. Advanced/Lowed Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN\ is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD\ should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN\. CLK is only recognized if CEN\ is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3\ to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1\ and CE3\ to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1\ and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE\ is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN\ does not deselect the device, CEN\ can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. I/O- Synchronous The direction of the pins is controlled by OE\ and the internal control logic. When OE\ is asserted LOW, the pins can behave as outputs. When HIGH, DQa - DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of the write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE\. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to I/O- Synchronous DQ[31:0]. During write sequences, DPa is controlled by BWSa\, DPb is controlled by BWSb\, DPc is controlled by BWSc\, and DPd is controlled by BWSd\. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device. InputSynchronous InputSynchronous ADV/LD\ InputSynchronous CLK CE1\ CE2 CE3\ Input-Clock InputSynchronous InputSynchronous InputSynchronous OE\ InputAsynchronous CEN\ InputSynchronous DQa DQb DQc DQd DPa DPb DPc DPd MODE Input Strap Pin VDD VDDQ VSS NC AS5SS512K36 Rev. 0.2 04/09 Power Supply I/O Power Supply Power supply for the I/O circuitry. Ground --Ground for the device. Should be connected to the ground of the system. No connects. Pins are not internally connected. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SSRAM Austin Semiconductor, Inc. FUNCTIONAL OVERVIEW The AS5SS512K36 is a Synchronous Flow-Through Burst NoBL SRAM designed specifically to eliminate wait states during WriteRead transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the clock enable input signal (CEN\). If CEN\ is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN\. Accesses can be initiated by asserting chip enables (CE1\, CE2, CE3\) active at the rising edge of the clock. If clock enable (CEN\) is active LOW and ADV/LD\ is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the write enable (WE\). Byte Write selects can be used to conduct byte write operations. Write operations are qualified by the write enable (WE\). All writes are simplified with on-chip synchronous self-timed write circuitry Synchronous chip enable (CE1\, CE2, and CE3\) and an asynchronous output enable (OE\) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD\ should be driven LOW once the device has been deselected in order to load a new address for the next operation. AS5SS512K36 Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN\ is asserted LOW, (2) CE1\, CE2, and CE3\ are ALL asserted active, (3) the write enable input signal WE is deasserted HIGH, and 4) ADV/LD\ is asserted LOW. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 7.5 ns (117-MHz device) provided OE\ is active LOW. After the first clock of the read access the output buffers are controlled by OE\ and the internal control logic. OE\ must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The AS5SS512K36 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD\ must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD\ will increment the internal burst counter regardless of the state of chip enables inputs or WE\. WE\ is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN\ is asserted LOW, (2) chip enables asserted active, and (3) the write signal WE\ is asserted LOW. The address presented is loaded into the address register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE\ input signal. This allows the external logic to present the data on DQ and DP. On the next clock rise the data presented to DQ and DP (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by Byte Write select signals. The AS5SS512K36 provide byte write capability that is described in the Write Cycle Description table. Asserting the write enable input (WE\) with the selected Byte Write select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the AS5SS512K36 are common I/O devices, data should not be driven into the device while the outputs are active. The output enable (OE\) can be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DP are automatically three-stated during the data portion of a write cycle, regardless of the state of OE\. Burst Write Accesses The AS5SS512K36 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD\ must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD\ is driven HIGH on the subsequent clock rise, the chip enables (CE1\, CE2, and CE3\) and WE\ inputs are ignored and the burst counter is incremented. The correct BWSa,b,c,d\ / BWSa,b\ inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE\s, ADSP\, and ADSC\ must remain inactive for the duration of tZZREC after the ZZ input returns LOW. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SSRAM Austin Semiconductor, Inc. CYCLE DESCRIPTION TRUTH TABLE1,2,3,4,5,6 OPERATION ADDRESS CE\ Deselected Suspend Begin Read Begin Write External --External External 1 X 0 0 CEN\ ADV/LD\ WE\ BWSx\ CLK 0 1 0 0 0 X 0 0 X X 1 0 X X X Valid L-H L-H L-H L-H DESCRIPTION I/Os three-state following next recognized clock. Clock ignored, all operations suspended. Address latched. Address latched, data presented two valid clocks later. Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWSa,b,c,d\/BWSa,b\. AS5SS512K36 Burst READ Operation Internal X 0 1 X X L-H Burst WRITE Operation Internal X 0 1 X Valid L-H INTERLEAVED BURST SEQUENCE FIRST SECOND THIRD FOURTH ADDRESS ADDRESS ADDRESS ADDRESS A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST SEQUENCE FIRST SECOND THIRD FOURTH ADDRESS ADDRESS ADDRESS ADDRESS A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 NOTES: 1. X = "Don't Care," 1 = Logic HIGH, 0 = Logic LOW, CE\ stands for ALL Chip Enables. CE\ = 0 stands for ALL Chip Enables are active. 2. Write is defined by WE\ and BWSx\. BWSx\ = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE\ signal. 4. CEN\ = 1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE\. 6. OE\ assumed LOW. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SSRAM Austin Semiconductor, Inc. ZZ MODE ELECTRICAL CHARACTERISTICS PARAMETER IDDZZ tZZS tZZREC DESCRIPTION Sleep mode stand-by current Device operation to ZZ ZZ recovery time CONDITIONS ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V 2t CYC MIN MAX 60 2t CYC UNITS mA ns ns AS5SS512K36 WRITE CYCLE DESCRIPTION1 FUNCTION Read Write - No Bytes Written Write Byte 0 - (DQa and DPa) Write Byte 1 - (DQb and DPb) Write Bytes 1, 0 Write Byte 2 - (DQc and DPc) Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - (DQb and DPd) Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes NOTES: 1. X = "Don't Care," 1 = Logic HIGH, 0 = Logic LOW. WE\ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWSd\ X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BWSc\ X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BWSb\ X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 BWSa\ X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SSRAM Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Supply Voltage on VDD Relative to GND ...................-0.5V to +3.6V Storage Temperature.............................................-65C to +150C Ambient Temperature with Power Applied..............-55C to +125C DC Voltage Applied to Outputs in High Z State1....................................................-0.5V to VDDQ +0.5V DC Input Voltage1................................................-0.5V to VDDQ +0.5V Current into Outputs (LOW)......................................................20mA Static Discharge Voltage..........................................................>2001V (per MIL-STD-883, Method 3015) Latch-Up Current.....................................................................>200mA AS5SS512K36 *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE AMBIENT TEMPERATURE2 Military (XT) -55C to +125C RANGE Industrial (IT) -40C to +85C VDD VDDQ 3.3V 2.5 - 5% to VDD +10%/-5% ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER Power Supply Voltage I/O Supply Voltage Output HIGH Voltage SYM VDD VDDQ VDD = MIN, IOH = -1.0mA VOH VDD = MIN, IOH = -4.0mA VDDQ = 23.3V VDD = MIN, IOL = 1.0mA Output LOW Voltage VOL VDD = MIN, IOL = 8.0mA Input HIGH Voltage VIH VDDQ = 23.3V 1 CONDITIONS MIN 3.135 2.375 VDDQ = 2.5V 2.0 2.4 -7.5 MAX 3.63 VDD MIN 3.135 2.375 2.0 2.4 -8.5 MAX 3.63 VDD UNIT V V V V VDDQ = 2.5V VDDQ = 23.3V VDDQ = 2.5V 2 1.7 -0.3 -0.3 -5 -30 0.4 0.4 VDD + 0.3 VDD + 0.3 0.8 0.7 5 30 5 210 2 1.7 -0.3 -0.3 -5 -30 -5 0.4 0.4 VDD + 0.3 VDD + 0.3 0.8 0.7 5 30 5 190 V V V V V V A A A mA VDDQ = 2.5V VIL VDDQ = 23.3V GND < VI < VDDQ IX Input LOW Voltage Input Load Current Input Current of MODE Output Leakage Current VDD Operating Supply IOZ IDD GND < VI < VDDQ, Output Disabled VDD = MAX, IOUT = 0mA, f = fMAX = 1/tCYC -5 Automatic CE Power-Down Current - TTL Inputs Automatic CE Power-Down Current - CMOS Inputs MAX VDD, Device Deselected, ISB1 VIN > VIH or VIN < VIL f = fMAX = 1/tCYC MAX VDD, Device Deselected, ISB2 VIN < 0.3V or VIN > VDDQ - 0.3V, f = 0 MAX VDD, Device Deselected, or 70 70 mA 120 110 mA Automatic CE Power-Down Current - CMOS Inputs ISB3 VIN < 0.3V or VIN > VDDQ - 0.3V, f = fMAX = 1/tCYC 105 90 mA Automatic CE Power-Down Current - TTL Inputs NOTES: MAX VDD, Device Deselected, ISB4 VIN > VIH or VIN < VIL f = 0 80 80 mA 1. Minimum voltage equals .2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SSRAM Austin Semiconductor, Inc. CAPACITANCE1 PARAMETER Input Capacitance Clock Input Capacitance Input/Output Capacitance SYM CIN CCLK CI/O TA = 25C, f = 1MHz TEST CONDITION MAX TBD TBD TBD UNIT pF pF pF AS5SS512K36 AC TEST LOADS & WAVEFORMS THERMAL RESISTANCE1 PARAMETER Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) CONDITIONS SYM JA Still air, soldered on a 3 x 4.5 inch sq., 2 layer printed circuit board. JC MAX 31 UNIT C/W 6 C/W NOTES: 1. Tested initially and after any design or process change that may affect these parameters. 2. Input waveform should have a slew rate of < 1 V/ns. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SSRAM Austin Semiconductor, Inc. -7.5 PARAMETER CLOCK Clock Cycle Time Clock HIGH Clock LOW OUTPUT TIMES Data Output Valid After CLK Rise OE\ LOW to Output Valid1, 3, 5 Data Output Hold After CLK Rise Clock to High-Z1-5 Clock to Low-Z1-5 OE\ HIGH to Output High-Z2, 3, 5 OE\ LOW to Output Low-Z2, 3, 5 SET-UP TIMES Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise CEN\ Set-up Before CLK Rise WE\, BWSx\ Set-up Before CLK Rise ADV/LD\ Set-up Before CLK Rise Chip Select Set-up HOLD TIMES Address Hold After CLK Rise Data Input Hold After CLK Rise CEN\ Hold After CLK Rise WE\, BWSx\ Hold After CLK Rise ADV/LD\ Hold After CLK Rise Chip Select Hold After CLK Rise NOTES: 1. Tested initially and after any design or process change that may affect these parameters. 2. Unless otherwise noted, test conditions assume signal transition time of 1ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to 3.0/2.5V for 3.3/2.5V VDDQ respectively, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads. 3. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 4. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 5. This parameter is sampled and not 100% tested. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS5SS512K36 SWITCHING CHARACTERISTICS (Over the Operating Range)2 -8.5 MAX MIN 8.5 2.3 2.3 MAX UNITS ns ns ns SYM tCYC tCH tCL MIN 7.5 2.1 2.1 tCO tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ 0 2.0 2.0 6.5 3.2 2.0 4.0 2.0 4.0 0 7.5 3.4 ns ns ns 4.0 ns ns 4.0 ns ns tAS tDS tCENS tWES tALS tCES 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns tAH tDH tCENH tWEH tALH tCEH 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns 9 SSRAM Austin Semiconductor, Inc. AS5SS512K36 SWITCHING WAVEFORMS: READ/WRITE/DESELECT SEQUENCE WE\ is the combination of WE\ & BWSx\ (x=a, b, c, d) to define a write cycle (see Write Cycle Description table). CE\ is the combination of CE1\, CE2, and CE3\. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SSRAM Austin Semiconductor, Inc. SWITCHING WAVEFORMS: BURST SEQUENCES AS5SS512K36 The combination of WE\ & BWSx\ (x=a, b, c, d) define a write cycle (see Write Cycle Description table). CE\ is the combination of CE1\, CE2, and CE3\. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN\ held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx\ input signals. Burst order determined by the state of the MODE input. CEN\ held LOW. OE\ held LOW. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SSRAM Austin Semiconductor, Inc. SWITCHING WAVEFORMS: OE\ TIMING AS5SS512K36 *All measurements are in inches. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SSRAM Austin Semiconductor, Inc. AS5SS512K36 MECHANICAL DEFINITIONS* ASI 100-PIN TQFP (Package Designator DQ) NOTES: * Dimensions are in millimeters. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 SSRAM Austin Semiconductor, Inc. AS5SS512K36 ORDERING INFORMATION EXAMPLE: AS5SS512K36DQ-7.5/IT Package Type DQ DQ Device Number AS5SS512K36 AS5SS512K36 Speed ns -7.5 -8.5 Process 1 /IT /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range -40oC to +85oC -55oC to +125oC NOTES: 1. The -7.5 option is available with IT processing only. AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 SSRAM Austin Semiconductor, Inc. DOCUMENT TITLE AS5SS512K36 512K x 36 SSRAM REVISION HISTORY Rev # 0.2 History Updated Speeds, pg 1&2 Release Date April 2009 Status Release AS5SS512K36 Rev. 0.2 04/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 |
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